1. Field of the Invention
The invention relates in general to a thin film transistor (TFT) array and manufacturing method thereof, and more particularly to a thin film transistor array having a high opening rate and fabricating method thereof.
2. Related Art of the Invention
A thin film transistor (TFT) liquid crystal display (LCD) is constructed of at least a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer. The thin film transistor array substrate is composed of a plurality thin film transistors arranged in an array, in which each one of the thin film transistors are disposed with a corresponding pixel electrode. The thin film transistor described above includes a gate, a channel layer, a drain and a source. The thin film transistor is provided as a switching device of the liquid crystal display unit.
The operation principle of the thin film transistor device is similar to that of a conventional MOS device, in which both of them includes three terminals (gate, drain and source). In general, a thin film transistor device can be classified into two types, one is an amorphous silicon type and the other is an poly-silicon type, in which the amorphous silicon thin film transistor is more fully developed than the others. With respect to an amorphous silicon thin film transistor liquid crystal display (LCD), the process flow of manufacturing thereof at least includes forming a gate, a channel layer, a source/drain, a pixel electrode and a cover layer over the substrate.
FIG. 1 is a top view illustrating a conventional thin film transistor array, and FIG. 1A to FIG. 1E are cross-sectional views illustrating a process flow chart of a method of forming a thin film transistor array substrate.
Referring to FIG. 1 and FIG. 1A, first of all, a substrate 100 is provided. Next, a first masking process is performed to form a gate 12 and a scan line 20 connecting to the gate 12. In the meantime, a bonding pad 24 is formed at the terminal of the scan line 20, and then a gate dielectric layer 50 is formed over the substrate 10.
Referring to FIG. 1 and FIG. 1B, a second masking process is performed to form a channel layer 14 and an ohm contact layer 15 on the gate dielectric layer 50 over the gate 12.
Referring to FIG. 1 and FIG. 1C, a third masking process is performed to form source/drain 16a/16b and a data line 22 connecting to the source 16a, and another bonding pad 26 is formed at the terminal of the data line 22.
Referring to FIG. 1 and FIG. 1D, a fourth masking process is performed to form a patterned cover layer 52 over the substrate 10 for exposing the drain 16b. The bonding pad 26 and the gate dielectric layer 50 are located at an upper level with respect to the bonding pad 24.
Referring to FIG. 1 and FIG. 1E, a fifth masking process is performed to form a patterned low dielectric photoresist layer 54 over the cover layer 52 for exposing portions of the drain 16b and the bonding pads 26, 24 (exposure of bonding pad 24 not shown). Then, the gate dielectric layer 50 on the bonding pad 24 is removed by using the photoresist layer 54 as an etching mask. Thereafter, a sixth masking process is performed to form pixel electrode 30 on the photoresist layer 54, and to cover indium zinc oxide (IZO) layers 32, 34 over the surface of the bonding pads 26, 24.
The purpose of forming a low dielectric photoresist layer above the cover layer is to enhance the opening rate of the liquid crystal display. Because of the existence of the low dielectric photoresist layer, the pixel electrode is extended to cover a portion of the data line to enhance the opening rate. It is noted that the thickness of the low dielectric photoresist layer is thick enough, therefore the parasitic capactiance between the pixel electrode and the data line is reduced, and the electrical property of the LCD panel will not be influenced.
However, in the method described above, after a patterned cover layer is provided in a masking process, then another masking process is provided for patterning the low dielectric photoresist layer. Therefore, one more masking process is required, and therefore the process is more complicated. Moreover, if the above process were to be simplified applying a masking process for patterning the low dielectric photoresist layer with one etching step, however in the resulting structure the bonding pad 26 would remain exposed and unprotected. Therefore in the subsequent step, the surface of the bonding pad 26 may get damaged due to its exposure to the reactant used in the subsequent process, for example, the developer and the etching chemicals, and also during the steps of forming a low dielectric photoresist layer 54 and then etching the gate dielectric layer 50 above the bonding pad 24.